Verifying Synchronization Strategies

Over the years, there have been numerous methods proposed to solve the synchronization problem. Many of these methods, however, are not sufficiently evaluated before being utilized leading to problems in a system design that are difficult to diagnose and solve. Therefore, it is crucial that strategies for synchronization are critically analyzed and verified before being incorporated in a system design. This paper reviews a number of the known methods for synchronization, discusses issues in their design, and presents techniques for their verification. 1 The Synchronization Problem While there have been many promising asynchronous design examples [48, 4, 17, 42, 1], asynchronous design is still not seeing widespread use. One important reason for this is that asynchronous designs must communicate with other parts of the system which typically operate synchronously. Unfortunately, this is difficult to do reliably without substantial latency penalties. When this latency penalty is taken into account, most, if not all, of the performance advantage gained by an asynchronous design is lost. Even if no asynchronous modules are used, synchronous modules operating at different clock rates or out of phase can have the same problem. The latter problem is becoming more significant as it becomes increasingly difficult to distribute a single global clock to all parts of the chip. Many designers today are considering the necessity of having multiple clock domains on a single chip, and they will need to face this problem. A synchronization problem can occur when a synchronous circuit must synchronize an asynchronous input. This can be done using a single D-type flip-flop as shown in Figure 1(a). However, if the clock edge arrives too close in time to data arriving from an asynchronous circuit, the circuit may enter a metastable state in which its output is at neither a logic 0 or logic 1 level, but rather, lies somewhere in between. This behavior is depicted in Figure 1(b). Assume that Q is initially low and that D has recently gone high. If D goes low again at about the same time that CLK rises, the output Q may start to rise and then get stuck between the logic levels as it observes D falling. Should Q rise or fall? Actually, either answer would be okay, but the flip-flop becomes indecisive. At some point, Q may continue to a logic 1 level, or it may drop to the logic 0 level. When this happens, however, is theoretically unbounded. If during this period of indecision, a ⋆ This research is supported by SRC contract 2002-TJ-1024.